1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a mask read-only memory (mask ROM).
2. Description of the Related Art
Read-only memory (ROM) is a type of non-volatile memory that retains data even when the power is off. In fact, non-volatile memory is essential for starting up most computer-controlled electronic products before operating in a normal state.
Mask ROM is one of the most basic types of non-volatile memory. To facilitate fabrication, the transistor within each memory unit is usually formed first. Metallic lines for connecting to the transistor are subsequently laid by a forming a photomask layer. Alternatively, metallic lines for connecting to the transistor are already formed and an ion implantation is subsequently carried out using a patterned photomask to adjust the threshold voltage of some of the transistors. Such programming of a mask ROM through an ion implantation process is also known as code implantation.
According to the aforementioned method of fabricating a mask ROM, very few modifications are needed to accommodate some changes in product requirement. Changes can be made simply by fabricating a new set of photomasks. Hence, the method is particularly suitable for mass production. To shorten delivery time to customers, it is possible to fabricate the mask ROM to the stage prior to programming and then store them as semi-finished product. Later, when the desired program code arrives, a code implantation of the semi-finished mask ROM and some other finishing steps can be carried out.
At present, other types of memory or logic devices and a mask ROM are also integrated together to increase chip performance. For example, an embedded static random access memory (embedded SRAM) and a mask ROM are integrated together.
In general, most static random access memory (SRAM) requires two metallic layers. The metallic layers are formed in a metallization process. Conventionally, the code implantation for adjusting the threshold voltage of transistors is conducted before the formation of an inter-layer dielectric (ILD) layer. Since the photomask necessary for carrying out code implantation can be fabricated only after customer's order is received, the metallization process for SRAM is performed in the very last stage. Because a metallization process takes time, product shipment to customer must be delayed.
To shorten customer delivery time, attempts have been made to perform the necessary metallization process of the SRAM before the code implantation necessary for adjusting the threshold voltages of various mask ROM devices is carried out.
FIG. 1 is a graph showing the threshold voltage versus thickness of inter-layer dielectric (ILD) layer after chemical-mechanical polishing and code implantation.
In a metallization process, a planarization of the inter-layer dielectric (ILD) layer and the inter-metal dielectric (IMD) layer is necessary. In general, the ILD and the IMD layer are planarized by chemical-mechanical polishing (CMP). However, chemical-mechanical polishing produces a variation of thickness between the ILD and the IMD layer of more than 1000 .ANG.. Variation of such magnitude can lead to imprecise adjustment of threshold voltage of devices in a code implantation of the mask ROM, thereby narrowing the coding window and increasing the level of difficulties in processing.
FIG. 2 is a graph with two curves showing the respective device saturation current (I.sub.dSat) versus amount of overlapping in photolithographic operation for a code implantation conducted before and after the formation of the inter-layer dielectric (ILD) layer.
In FIG. 2, the curve linked by solid diamonds represents the relationship between device saturated current and the amount of overlapping in photolithographic operation for code implantation performed after the formation of the inter-layer dielectric (ILD) layer. On the other hand, the curve linked by solid squares represents the relationship between device saturated current and the amount of overlapping in photolithographic operation for code implantation performed before the formation of the ILD layer.
As shown in FIG. 2, it does not matter if the code implantation is carried out before or after the ILD layer is formed; saturated current decreases when the amount of overlapping increases. However, under the same overlapping conditions, performing a implantation after the formation of the ILD layer produces a smaller saturated current than performing a code implantation before the formation of the ILD layer.
This is because when the feature size of a mask ROM is smaller than 0.35 .mu.m, the scattering effect in a code implantation is intensified. Since both the ILD layer and the IMD layer have a definite thickness, a portion of the ion beam used in the code implantation may be blocked. However, using a high-energy ion beam in code implantation can lead to heavy scattering, ultimately leading to a fall in device saturated current as well as an increase in device switching problems.
In the meantime, as feature size of devices within a mask ROM falls below 0.35 .mu.m, the photolithographic operation needed to prepare for code implantation is harder to control. Overlapping occurs more often, leading to further lowering of device saturated current and more device reliability problems.